Part Number Hot Search : 
AHA4011C A01BB 103LF 2SC18 61J11 RMPA0966 S6A0075 X193XX
Product Description
Full Text Search
 

To Download SY100EP15VK4G-TR Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
  1 ecl pro sy100ep15v micrel, inc.m9999-120505 hbwhelp@micrel.com or (408) 955-1690 the sy100ep15v is a high-speed, low-skew, pecl/ecl 1:4 precision fanout buffer with a 2:1 mux front end in asmall 16-pin tssop package. the 2:1 mux input accepts a single-ended pecl/ecl source (clk1) and a differential pecl/ecl/hstl source (clk0). all i/o pins are 100k ep pecl/ecl logic compatible. ac performance is guaranteed over the industrial ?0 c to +85 c temperature range and 3.3v to 5v supply voltage. this device will operate in pecl/lvpecl or ecl/lveclmode. for clock applications, the high-speed design combined with an extremely fast rise/fall time of less than 225ps produces a toggle frequency as high as 2.5ghz (~400mv pp swing). a v bb output reference pin is available for ac?oupled and single-ended input applications. in addition, asynchronous output enable function is provided. the sy100ep15v is part of micrel? high-speed, precision edge timing and distribution family. for applications thatrequire a different i/o combination, consult micrel's website at www.micrel.com, and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock dividers. all support documentation can be found on micrel? web site at: www.micrel.com. features description rev.: e amendment: /0 issue date: december 2005 ecl pro sy100ep15v high-speed 1:4 pecl/ecl fanout buffer 2:1 multiplexer input guaranteed ac parameters over temp/voltage: > 2.5ghz f max (toggle) < 225ps rise/fall times < 25ps within device skew < 425ps propagation delay (clk-to-q) low jitter design: < 1ps rms cycle-to-cycle jitter < 20ps pp total jitter flexible power supply: 3.3v/5v wide operating temperature range: ?0 c to +85 c v bb reference for ac-coupled or single-ended applications output enable/disable function 100k pecl/ecl compatible logic input accepts pecl/lvpecl/ecl/hstl logic levels available in a 16-pin tssop package 3.3v/5v 2.5ghz pecl/ecl 1:4 fanout buffer with 2:1 input mux ecl pro ecl pro is a trademark of micrel, inc. downloaded from: http:///
2 ecl pro sy100ep15v micrel, inc.m9999-120505 hbwhelp@micrel.com or (408) 955-1690 package/ordering information ordering information (1) package operating package lead part number type range marking finish sy100ep15vk4c k4-16-1 commercial xep15v sn-pb sy100ep15vk4ctr (2) k4-16-1 commercial xep15v sn-pb sy100ep15vk4i k4-16-1 industrial xep15v sn-pb sy100ep15vk4itr (2) k4-16-1 industrial xep15v sn-pb sy100ep15vk4g (3) k4-16-1 industrial xep15v with nipdau pb-free bar-line indicator pb-free sy100ep15vk4gtr (2, 3) k4-16-1 industrial xep15v with nipdau pb-free bar-line indicator pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25 c, dc electricals only. 2. tape and reel. 3. pb-free package is recommended for new designs. available in 16-pin tssop (k4-16-1) 1 q0 /q0 q1 /q1 q2 /q2 q3 /q3 16 vcc/en clk1 vbb /clk0 clk0sel vee 21 5 31 4 41 3 51 2 61 1 71 0 89 d q 10 downloaded from: http:///
3 ecl pro sy100ep15v micrel, inc.m9999-120505 hbwhelp@micrel.com or (408) 955-1690 truth table (1) clk0 clk1 sel /en q lx lll hx l lh xl hll xh hlh xlhl x hhl pin description pin pin number function 1, 2, 3, 4 q0 ?q3 outputs 0 through 3: 100kep (lv)pecl/(lv)ecl compatible differential outputs. terminate 5, 6, 7, 8 /q0 ?/q3 with 50 ? to v cc ?v. unused output pairs may be left floating, or pulled-down with a 2k ? resistor to the most negative supply. unused single-ended outputs must have a balanced load.for ac-coupled applications, the output stage emitter follower must have a dc current path to ground. see ?ermination?section. 9 vee negative power supply: for pecl/lvpecl applications, connect to gnd. 10 sel 100kep (lv)pecl/(lv)ecl compatible 2:1 mux input select control. see ?ruth table.?the select (sel) pin includes an internal 75k ? pull-down resistor. default condition when left floating is low, and clk0 input is selected. 11, 12 clk0, /clk0 differential (lv)pecl/(lv)ecl/hstl compatible input: the inputs include an internal 75k ? pull-down resistor on clk0 and internal 75k ? pull-up and pull-down on /clk0. default condition for clk0 is low when left floating and v cc /2 for /clk0 when left floating. 13 vbb reference output voltage: this reference is typically used to bias the unused inverting input for single-ended input applications, or as the termination point for ac-coupled differential inputapplications. v bb reference value is approximately v cc ?.3v, and tracks vcc 1:1. maximum sink/source capability for v bb is 0.50ma. for single ended inputs, connect to the unused input through a 50 ? resistor. decouple the v bb pin with a 0.01 f capacitor to v cc . 14 clk1 single-ended (lv)pecl/(lv)ecl compatible input: this pin includes an internal 75k ? pull-down resistor. default condition is low when left floating. 15 /en 100kep (lv)pecl/(lv)ecl compatible input: this synchronous pin controls the output state. see ?ruth table.? to ensure proper synchronous operation, adhere to the set-up and holdtimes, as described in the ac electrical table. when /en pin goes high, q outputs go low, and /q outputs go high on the next falling clock transition. this synchronous operation avoids any chance of generating a runt pulse. 16 vcc positive power supply: bypass with 0.1 f//0.01 f low esr capacitors. note:1. = negative edge. downloaded from: http:///
4 ecl pro sy100ep15v micrel, inc.m9999-120505 hbwhelp@micrel.com or (408) 955-1690 symbol rating value unit v cc ? ee power supply voltage 6.0 v v in input voltage (v cc = 0v, v in not more negative than v ee ) ?.0 to 0 v input voltage (v ee = 0v, v in not more positive than v cc ) +6.0 to 0 i out output current ?ontinuous 50 ma ?urge 100 i bb v bb sink/source current (2) 0.5 ma t lead lead temperature (soldering, 20sec.) +260 c t a operating temperature range ?0 to +85 c t store storage temperature range ?5 to +150 c ja package thermal resistance ?till-air (single-layer pcb) 115 (junction-to-ambient) ?till-air (multi-layer pcb) 75 c/w ?00lfpm (multi-layer pcb) 65 jc package thermal resistance 21 c/w (junction-to-case) notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ratlng conditions for extended periods may affect device reliability. 2. due to the limited drive capability, use for inputs of same package only. absolute maximum ratings (1) t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v cc power supply voltage v (pecl) 4.5 5.0 5.5 4.5 5.0 5.5 4.5 5.0 5.5 (lvpecl) 2.97 3.3 3.63 2.97 3.3 3.63 2.97 3.3 3.63 (ecl) ?.5 ?.0 ?.5 ?.5 ?.0 ?.5 ?.5 ?.0 ?.5 (lvecl) ?.63 ?.3 ?.97 ?.63 ?.3 ?.97 ?.63 ?.3 ?.97 i cc power supply current 70 52 72 75 ma i ih input high current 150 150 150 av in = v ih i il input low current clk0, clk1 0.5 0.5 0.5 av in = v il /clk0 ?50 ?50 ?50 av in = v il c in input capacitance (tssop) 1 . 0p f note: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. dc electrical characteristics (1) downloaded from: http:///
5 ecl pro sy100ep15v micrel, inc.m9999-120505 hbwhelp@micrel.com or (408) 955-1690 t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage 1355 1675 1355 1675 1355 1675 mv v cc = 3.3v (single-ended) v ih input high voltage 2075 2420 2075 2420 2075 2420 mv v cc = 3.3v (single-ended) v ol output low voltage 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v cc = 3.3v v oh output high voltage 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v cc = 3.3v v bb reference voltage (2) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v cc = 3.3v v ihcmr input high voltage 1.2 v cc 1.2 v cc 1.2 v cc v common mode range (3) notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. input and output parameters varies 1:1 with v cc . output load is 50 ? to v cc ?v. 2. v bb varies 1:1 with v cc . 3. the v ihcmr range is referenced to the most positive side of the differential input signal. (100kep) lvpecl dc electrical characteristics (1) v cc = 3.0v 10%, v ee = 0v t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage 3055 3375 3055 3375 3055 3375 mv v cc = 5v (single-ended) v ih input high voltage 3775 4120 3775 4120 3775 4120 mv v cc = 5v (single-ended) v ol output low voltage 3055 3180 3305 3055 3180 3305 3055 3180 3305 mv v cc = 5v v oh output high voltage 3855 3980 4105 3855 3980 4105 3855 3980 4105 mv v cc = 5v v bb output voltage reference (2) 3475 3575 3675 3475 3575 3675 3475 3575 3675 mv v cc = 5v v ihcmr input high voltage (3) 1.2 v cc 1.2 v cc 1.2 v cc v common mode range notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. input and output parameters varies 1:1 with v cc . output load is 50 ? to v cc ?v. 2. v bb varies 1:1 with v cc . 3. the v ihcmr range is referenced to the most positive side of the differential input signal. (100kep) pecl dc electrical characteristics (1) v cc = 5.0v 10%, v ee = 0v downloaded from: http:///
6 ecl pro sy100ep15v micrel, inc.m9999-120505 hbwhelp@micrel.com or (408) 955-1690 t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage ?945 ?625 ?945 ?625 ?945 ?625 mv (single-ended) v ih input high voltage ?165 ?80 ?165 ?80 ?165 ?80 mv (single-ended) v ol output low voltage ?945 1820 ?695 ?945 ?820 ?695 ?945 ?820 ?695 mv 50 ? to v cc ?v v oh output high voltage ?145 1020 ?95 ?145 ?020 ?95 ?145 ?020 ?95 mv 50 ? to v cc ?v v bb output reference voltage ?525 1425 ?325 ?525 ?425 ?325 ?525 ?425 ?325 mv v ihcmr input high voltage v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 v common mode range (2) notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. 2. the v ihcmr range is referenced to the most positive side of the differential input signal. (100kep) lvecl dc electrical characteristics (1) v cc = 0v, v ee = ?.97v to ?.63v (100k) ecl dc electrical characteristics (1) v cc = 0v, v ee = ?.5v to ?.5v t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage ?945 ?625 ?945 ?625 ?945 ?625 mv v ih input high voltage ?225 ?80 ?225 ?80 ?225 ?80 mv v ol output low voltage ?945 1820 ?695 ?945 ?820 ?695 ?945 ?820 ?695 mv 50 ? to v cc ?v v oh output high voltage ?145 1020 ?95 ?145 ?020 ?95 ?145 ?020 ?95 mv 50 ? to v cc ?v v bb output reference voltage ?525 1425 ?325 ?525 ?425 ?325 ?525 ?425 ?325 mv v ihcmr input high voltage v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 v common mode range (2) notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. 2. the v ihcmr range is referenced to the most positive side of the differential input signal. t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit v ih input high voltage 1200 1200 1200 mv v il input low voltage 400 400 400 mv hstl input dc electrical characteristics v cc = 2.97v to 3.63v, v ee = 0v downloaded from: http:///
7 ecl pro sy100ep15v micrel, inc.m9999-120505 hbwhelp@micrel.com or (408) 955-1690 t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit f max (1) maximum frequency 2.5 2.5 2.5 ghz t pd propagationdelay to outputpecl/ecl diff. in-to-q 275 425 275 375 425 275 425 ps in (single-ended)-to-q 250 450 250 400 450 250 450 ps sel-to-q 250 450 250 400 450 250 450 ps lvpecl/lvecl diff. in-to-q 275 425 275 375 425 275 425 ps in (single-ended)-to-q 250 450 250 400 450 250 450 ps sel-to-q 250 450 250 400 450 250 450 ps t skew (2) within-device skew (diff.) 25 15 25 25 ps part-to-part skew (diff.) 150 100 150 150 ps t s (3) set-up time /en to clk 100 0 100 0 100 0 ps t h (3) hold time /en to clk 200 50 200 50 200 50 ps t jitter cycle-to-cycle jitter (4) 0.2 1 0.2 1 0.2 1 ps rms total jitter (622mhz clock) (5) <20 <20 <20 ps pp v id input voltage range 150 800 1200 150 800 1200 150 800 1200 mv t r , t f output rise/fall times 75 225 75 130 225 85 225 ps (20% to 80%) notes: 1. f max is defined as the maximum toggle frequency. measured with 750mv input signal, 50% duty cycle, output swing 400mv(diff), all loading with 50 ? to v cc ?v. 2. skew is measured between outputs under identical transitions. 3. set-up and hold times apply to synchronous applications that intend to enable/disable before then ext clock cycle. for asynchronous applications, set-up and hold time does not apply. 4. cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. t jitter_cc =t n ? n+1 where t is the time between rising edges of the output signal. 5. total jitter definition: with an ideal clock input applied to one channel of the mux, no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to-peak jitter value. ac electrical characteristics lvpecl: v cc = 2.97v to 3.63v, v ee = 0v; pecl: v cc = 4.5v to 5.5v, v ee = 0v ecl: v cc = 0v, v ee = ?.5v to ?.5v; lvecl: v cc = 0v, v ee = ?.97v to ?.63v downloaded from: http:///
8 ecl pro sy100ep15v micrel, inc.m9999-120505 hbwhelp@micrel.com or (408) 955-1690 termination recommendations r282 ? r282 ? z o = 50 ? z o = 50 ? +3.3v +3.3v v t = v cc ?v r1130 ? r1130 ? +3.3v figure 1. parallel termination?hevenin equivalent notes: 1. for +2.5v systems: r1 = 250 ? , r2 = 62.5 ? . 2. for +5.0v systems: r1 = 82 ? , r2 = 130 ? . z = 50 ? z = 50 ? 50 ? 50 ? 50 ? +3.3v +3.3v ?ource ?estination r b (optional)c1 0.01 f figure 2. three-resistor ??ermination notes: 1. power-saving alternative to thevenin termination. 2. place termination resistors as close to destination inputs as possible. 3. r b resistor sets the dc bias voltage, equal to v t . for +3.3v systems r b = 46 ? to 50 ? . for +5v systems, r b = 110 ? . 4. c1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches. +3.3v +3.3v 50 ? z o = 50 ? 0.01 f v bb r282 ? +3.3v +3.3v r1130 ? r1130 ? r282 ? v t = v cc ?v q /q +3.3v figure 3. terminating unused i/o notes 1. unused output (/q) must be terminated to balance the output. 2. micrel? differential i/o logic devices include a v bb reference pin . 3. connect unused input through 50 ? to v bb . bypass with a 0.01 f capacitor to v cc , not gnd. 4. for +2.5v systems: r1 = 250 ? , r2 = 62.5 ? . downloaded from: http:///
9 ecl pro sy100ep15v micrel, inc.m9999-120505 hbwhelp@micrel.com or (408) 955-1690 16-pin tssop (k4-16-1) rev. 01 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this datasheet is believed to be accurate and reliable. however, no responsibility is assumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchaser? use or sale of micrel products for use in life support appliances, devices or systems is at purchaser? own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ?2005 micrel, incorporated. downloaded from: http:///


▲Up To Search▲   

 
Price & Availability of SY100EP15VK4G-TR

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X